Stress Characterization of Polycrystalline Silicon for Advanced CMOS Technologies

Abstract

As advanced integrated circuit manufacturing moves through the 65nm technology node, we find that polycrystalline silicon (Poly-Si) films can be engineered to modulate the strain in the underlying channel for improved NMOS transistor performance in addition to fulfilling this primary function as the CMOS gate electrodes. In this paper, we study how the deposition conditions for Poly-Si films change the intrinsic stress. The effect of subsequent processing steps, such as ion implantation and rapid thermal annealing (RTA), on the Poly-Si stress are also measured. Poly-Si films deposited with different conditions are characterized by secondary ion mass spectrometry (SIMS) and sheet resistance. The results show that the compressive stress of columnar Poly-Si films deposited using disilane as the precursor has been reduced by 50% compared with films deposited using silane for the precursor. The stress measurement results confirm that the implant energy modifies the poly-Si film stress: the higher the energy, the lower the compressive stress. The SIMS and sheet resistance data indicate that the deposition conditions can affect the final Poly-Si dopant activation.