Abstract
Grinding wafers is a well established process for thinning wafers down to 100 μm for use in smart cards and stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, the authors investigate the influence of the backside induced stress in ultra thin Si wafers (~20μm). Such aggressive thinning is a requirement for high density vias interconnect, stacked die packaging and flexible electronics.
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