Stress analysis of lead-free solders with under bump metallurgy in a wafer level chip scale package

Abstract

The wafer level chip scale assembly (WLCSP) has increasingly become popular due to its compact, wafer scale assembly. In a WLCSP assembly, the under bump metallurgy (UBM) connecting the solder joints and the chip is crucial for the assembly reliability. This study focuses on a WLCSP with 96.5Sn3.5Ag/95.5Sn3.8Ag0.7Cu solder joints and Ti/Cu/Ni UBM on a 2–layer microvia build-up electric board. Furthermore, the Garofalo-Arrhenius creep model in finite element analysis ANSYS 6.0 is used for simulations on the WLCSP assembly under thermal cycling to investigate the deformations of the assembly with different thickness of nickel layer, the maximum equivalent strain and maximum equivalent stress of microvias/joints. Finally, the Coffin-Manson equation is applied to predict the fatigue lives of four combinations of solder joints with different eutectic alloy and thickness of nickel layer.