Stress Analysis and Design Optimization for Low-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> Chip With Cu Pillar Interconnection

Abstract

Cu pillar technology can cater for high I/O, fine pitch, and miniaturization requirements compared with wire bonding and conventional solder flip-chip technologies. However, chip-package interaction of Cu pillar and low-k chip is a critical challenge during assembly process due to stiffer Cu pillar structure compared with conventional solder bump. Thermo-compression bonding (TCB) process was adopted and used for fine pitch Cu pillar assembly on Cu/low-k chip to reduce the package warpage and low-k stress. In this paper, a novel TCB process modeling methodology using a 2-D axisymmetric finite-element model with global-local technique was demonstrated by considering step-by-step process conditions. The TCB modeling method was validated by the experimental data. The simulation results show that TCB process results in much lower package warpage and low-k stress compared with conventional reflow (RF) process. Based on the proposed TCB modeling method, the comprehensive parametric studies were conducted to optimize TCB process and Cu pillar design for package reliability improvement, including bonding process conditions, Cu pillar structure design, package geometry, and packaging material selection. RF process-induced package warpage and low-k stress were also simulated for comparison. The final package and assembly solution was successfully achieved based on the suggestions and recommendations provided by the simulation results.