Abstract

This paper proposes a novel method for managing cache consistency in multi-core systems when executing stream applications. The method involves arranging a mark cache for private data caches, which includes an optional integrality descriptor for shared reading and writing data states and shared data manipulation positions. The integrality descriptor identifies the current mode of operation for shared data in the private data cache. Additionally, the method utilizes a two-dimensional array register, referred to as the shared data manipulation position, with width N and depth M, where N distinguishes between different cache blocks and locking territories, while M corresponds to the number of cache blocks. This enables the identification of the cache capable or block corresponding to shared data during read and write operations. The proposed method offers simplicity, ease of operation, low hardware implementation cost, good extensibility, and strong configurability, ultimately improving system effectiveness.

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