Strategic Design and Optimization of Vedic Low Pass FIR Filter for ECG Signals

Abstract

ECG signals are contaminated by numerous noise sources during signal acquisition and need to be filtered before any sort of analysis can be made. Although numerous filter implementations have been proposed in literature, the considerations to be made in VLSI design and implementation of filter are scattered over numerous papers. This paper aims to provide readers a systematic procedure to design Finite Impulse Response (FIR) filter architecture to filter high frequency noise from ECG signals. Crucial parameters in design of FIR filters viz. Choice of Window Technique, Cut-off and Sampling Frequencies, Order of the Filter, Number of Bits for representation, Stop Band attenuation etc. are discussed at length and strategic decisions are made based on experimentation. VLSI architectures based on Vedic sutras result in low power design which is desirable in portable equipments. This paper therefore presents Vedic Sutra Urdhva Tiryagbhyam based FIR Filter. Software tools used for this study include MATLAB (and its FDA tool) and Xilinx ISE 14.7. The Vedic FIR filter has been implemented targeted for Spartan-3e starter FPGA board. The proposed 64th order FIR filter architecture occupies 869 slices, 1483 4-input LUTs and consumes dynamic power of 80 μW at 100 MHz clock frequency.