Strained-Si heterostructure field effect devices: Strain-engineering in CMOS technology

Abstract

Meeting performance targets of 22 nm Si- CMOS and beyond, as per 2006 ITRS update, will require innovation at all levels of CMOS development, including new channel materials, device design, integration, circuit design, and system architecture. In new channel materials, some of the options under consideration include (a) local and global strain, (b) Si surface orientation, and (c) non-Si materials including Ge and III-Vs. This invited paper is focused to address present and future CMOS performance challenges via advanced materials and processes and discuss the latest developments in strain engineering in Si CMOS devices. The materials and device technology of MOSFETs utilizing strain- or stress-engineered heterostructure channels are also reviewed.