Strained silicon nanowire tunnel FETs and NAND logic

Abstract

We present strained Si TFETs with different architectures, from planar to highly down scaled gate all around (GAA) nanowire (NW) devices. Optimizing the TFET structure improves the electrostatics as required to enhance the tunneling currents. Furthermore, it suppresses trap assisted tunneling (TAT) and thus yields to steeper subthreshold slopes. We also demonstrate that a NAND Gate with GAA NW pTFET can be operated at VDD=0.2V. This demonstrates the great potential of TFETs for ultra low power application.