Strained silicon dynamic threshold voltage MOSFETs for low voltage and ultra high speed CMOS circuits

Abstract

With the rapid development of integrated circuit industry, the demand for low voltage operation and high speed of digital CMOS circuits is becoming inevitable. The Dynamic Threshold voltage (DT) technique emerged to extend lower bound of power supply, while the strained silicon technique stands out as a cost-effective way to improve circuit speed. In this work, the combination of Dynamic Threshold voltage technique with strained silicon technique is explored and demonstrated on bulk silicon substrate. The strained silicon DT NMOS exhibit a lower subthreshold swing of 66 mV/dec and a remarkably higher saturate drain current of 10.9X at VGS=0.5 V, compared to standard strained silicon NMOS. As the result of these improvements, the strained silicon DT-CMOS inverter remains eligible with the power supply voltage down to 0.3 V.