Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/high-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium.

Lu Xie,Ben Li,Kunpeng Jia,Junjie Li,Xuezheng Ai,Yongkui Zhang,Huilong Zhu,Zhenzhen Kong,Henry H Radamson,Guilei Wang,Liheng Zhao,Chen Li,Yangyang Li,Anyan Du,Xiaogen Yin

doi:10.3390/nano10091715

Abstract

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

Highlights

In recent years, with the continuous scaling-down of CMOS technology nodes, high-mobility channel materials (SiGe, Ge and III–V material such as InGaAs) and novel device designs (horizontally/vertically Gate-All-Around (GAA) stacked nanowires) have been under investigation [1–13]
The high mobility of n-GaN and the current possibility of achieving an enhancement mode in non-polar GaN have been extensively researched with gallium nitride Fin Field-Effect Transistors (FinFETs) [14,15]
We have studied the complete process of the formation of a 20 nm Ge channel layer in Vertical Gate-All-Around (VGAA) NWs, including the epitaxy and etching processes, with a focus on the selective etching of Ge relative to SiGe in Si0.2Ge0.8/Ge multilayers with HNO3 and H2O2 solution

Summary

Introduction

With the continuous scaling-down of CMOS technology nodes, high-mobility channel materials (SiGe, Ge and III–V material such as InGaAs) and novel device designs (horizontally/vertically Gate-All-Around (GAA) stacked nanowires) have been under investigation [1–13]. The growth of a high-quality Ge layer on Si is one of the main challenges in achieving a vertical GAA structure.

Results

Conclusion