Abstract
Strain technology under metal/high-k damascene-gate stacks is discussed. It is estimated from stress simulation that compressive stresses for pMOSFETs with compressive stress-liners of SiN film and eSiGe are enhanced by damascene-gate process. Moreover, it is confirmed by UV-Raman spectroscopy in plane view that the compressive stress is considerably enhanced just after dummy-gate removal step, especially for smaller gate length. On the other hand for nMOSFETs, tensile stresses even by top-cut tensile stress-liners of SiN film are slightly enhanced by damascene-gate process. Therefore, high drivability of high-performance CMOS devices with gate length of 40 nm are achieved by not only thinner Tinv of 1.4 nm but also higher transconductance.
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