Abstract
We compare solid phase epitaxial growth of amorphous Si–Ge alloys created by Ge ion implantation into Si with and without the imposition of 0.5GPa of externally applied biaxial tensile stress. External loading stabilizes the growth front against roughening, resulting in a doubling of the maximum reported Ge concentration for stable growth to 14at.%. The externally applied stress appears to superpose with the intrinsic compositional stress and indicates a threshold of approximately 0.6GPa for interface breakdown. This principle is expected to be applicable to expanding the composition range for stable growth of other semiconductor alloy combinations by other growth techniques.
Highlights
Band-gap engineering using compositionally or mechanically strained semiconductor layers has become a useful tool for device designers looking to extend the capabilities of Si-based semiconductor devices.1 As a result, an increasing number of Si-based architectures involving strained layers are being investigated for use in photonic and high-speed electronic devices.2 the strain introduced by the incorporation of Ge into the Si lattice can cause the formation of extended defects, and different fabrication techniques require different defect engineering approaches to reduce their impact
We present an approach for increasing the amount of Ge that can be incorporated into the lattice during SPEG while still maintaining a smooth interface
Figure 3͑awas taken from the outer portion of the sampleoutside the loading ringswhere the externally imposed stress was zero, whereas Fig. 3͑bwas taken from a portion annealed while under an externally applied biaxial tensile stress of +0.5 GPa
Summary
Band-gap engineering using compositionally or mechanically strained semiconductor layers has become a useful tool for device designers looking to extend the capabilities of Si-based semiconductor devices. As a result, an increasing number of Si-based architectures involving strained layers are being investigated for use in photonic and high-speed electronic devices. the strain introduced by the incorporation of Ge into the Si lattice can cause the formation of extended defects, and different fabrication techniques require different defect engineering approaches to reduce their impact. Band-gap engineering using compositionally or mechanically strained semiconductor layers has become a useful tool for device designers looking to extend the capabilities of Si-based semiconductor devices.. One technique for producing these alloys is ion implantation of Ge into a Si substrate and crystallization of the resulting amorphous surface layer by solid phase epitaxial growthSPEG. This process has been used to improve structural quality and enhance dopant activation.. This process has been used to improve structural quality and enhance dopant activation.4 With this method, the strain caused by the lattice mismatch places an upper limit of 3 – 7 at. This process has been used to improve structural quality and enhance dopant activation. With this method, the strain caused by the lattice mismatch places an upper limit of 3 – 7 at. % on the amount of Ge that can be incorporated into the Si lattice before interfacial breakdown into a rough growth front occurs, causing the generation of defects, such as111͖ facets and stacking faults, leading to severely degraded material not suitable for devices.
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