Strain mapping with nm-scale resolution for the silicon-on-insulator generation of semiconductor devices by advanced electron microscopy

Abstract

Strain engineering in the conduction channel is a cost effective method of boosting the performance in state-of-the-art semiconductor devices. However, given the small dimensions of these devices, it is difficult to quantitatively measure the strain with the required spatial resolution. Three different transmission electron microscopy techniques, high-angle annular dark field scanning transmission electron microscopy, dark field electron holography, and nanobeam electron diffraction have been applied to measure the strain in simple bulk and SOI calibration specimens. These techniques are then applied to different gate length SiGe SOI pFET devices in order to measure the strain in the conduction channel. For these devices, improved spatial resolution is required, and strain maps with spatial resolutions as good as 1 nm have been achieved. Finally, we discuss the relative advantages and disadvantages of using these three different techniques when used for strain measurement.