Strain Engineering of Nanoscale Si P-Type Metal-Oxide-Semiconductor Field-Effect Transistor Devices with SiGe Alloy Integrated with Contact-Etch-Stop Layer Stressors

Abstract

Strained-silicon (Si) has been incorporated into a leading nanoscale logic technology. By means of silicon-germanium (SiGe) alloy stressor embedded in source and drain (S/D) region, the performance of P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) is effectively enhanced. However, when a compressive contact-etch-stop layer (CESL) is combined, the stress interaction and relative impacts of SiGe stressor integrated with CESL on mobility enhancement has been little reported. Therefore, the research performs a three dimensional (3D) stress simulation evaluation based on finite element method (FEM) for PMOSFETs with S/D SiGe stressor and compressive CESL. The proposed simulation methodology is validated as compared with other technological literatures. In additions, the gate width dependency is systematically discussed to explore the stress effects on devices. The analysis results indicate that a -2.6 GPa CESL would continue boosting the stress magnitude on Si channel region except for a gate width smaller than 50 nm. The results are useful for nanoscale transistor while selecting a proper CESL in the manufacturing processes of advanced logic technologies.