Abstract
Silicon based complementary metal-oxide-semiconductor field-effect-transistor (CMOSFET) technology has continued to progress unabated for last five decades despite various challenges arising due to extreme scaling. Pervasive use of Si technology is evident in a large spectrum of products ranging from high end mainframe and server computers for businesses to laptops, smartphones, and internet of things (IoT) for consumer-oriented products. There is an ever-increasing demand to improve Si device performance for the above described and future products. Strain engineering is one of the key aspects to improve transistor performance. In this review, we describe strain engineering in silicon based advanced CMOS technology, which has evolved from conventional two-dimensional (2D) MOSFET structure to 3D FinFET structure. The impact of shrinking dimensions of scaled FinFETs on channel strain engineering as well as options for strain engineering in future CMOS architecture are described. Finally, strain engineering in non-silicon based functional materials such as gallium nitride (GaN) and 2D materials will be briefly discussed.
Highlights
Strain engineering refers to the mechanical deformation of a material for the purpose of improving one or more of its properties
A history of carrier mobility enhancement in 2D and 3D CMOS architectures by strain engineering is described
Since epitaxial growth of Si and SiGe is an integral part of FET channel and source-drain formation, controlling the structural quality of these epitaxial layers is at the heart of strain engineering technology
Summary
Strain engineering refers to the mechanical deformation of a material for the purpose of improving one or more of its properties. In the case of semiconductor materials, the most popular application of strain manipulation is to improve carrier transport and current drive in transistors. There has been a great deal of theoretical and experimental works performed in the field of carrier transport in strained semiconductors. A history of carrier mobility enhancement in 2D and 3D CMOS architectures by strain engineering is described
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