Abstract

We use depth-resolved cathodoluminescence spectroscopy (DRCLS), Kelvin probe force microscopy (KPFM), and surface photovoltage spectroscopy (SPS) on a nanometer scale to map the temperature, strain, and defects inside GaN high-electron-mobility transistors. DRCLS maps temperature at localized depths, particularly within the 2-D electron gas region during device operation. KPFM maps surface electric potential across the device, revealing lower potential patches that decrease rapidly with increasing off-state stress. CL spectra acquired at these patches exhibit defect emissions that increase with both on- and off-state stresses and that increase with decreasing surface potential. SPS also reveals features of deep level gap states generated after device operation that reduce near-band-edge emission and increase surface band bending. Our nanoscale measurements are consistent with defect generation by inverse piezoelectric field-induced stress at the gate edge on the drain side at high voltage.

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