Stochastic circuit synthesis via satisfiability

Abstract

Binary numbers converted into stochastic bitstreams enable computationally complex arithmetic to be performed using stochastic computing (SC). The fault-tolerant nature of stochastic computing has made it useful in a large number of applications. However, stochastic circuit synthesis allows for a larger solution space than classical logic synthesis. SC circuits are synthesized using heuristics in previous methods. In this paper, a novel exact synthesis method via satisfiability (SAT) is proposed to obtain an optimal SC circuit represented by majority-inverter graphs (MIGs). To accelerate the algorithm for executing the exact synthesis, we try to decompose the problem vector by using a cube assignment method for scalability. Moreover, we propose a hybrid algorithm based on both exact synthesis and heuristics. The experimental results indicate that the proposed hybrid approach can reduces the area by 14%, the delay by 9%, and the mean absolute error by 7%.