Steep Switching Hybrid Phase Transition FETs (Hyper-FET) for Low Power Applications: A Device-Circuit Co-design Perspective—Part II

Abstract

Hybrid-phase-transition FETs (Hyper-FETs) are recently proposed steep switching devices that utilize the phase transition materials (PTM) to achieve a boost in the ratio of ON ( ${I}_{{{\mathrm {ON}}}})$ and OFF currents ( ${I}_{{{\mathrm {OFF}}}})$ . Prototypical demonstrations of the Hyper-FET have shown performance improvement in comparison with conventional transistors, which motivates the evaluation of its device-circuit design space. In part I, we analyze the device aspects establishing the effects of the resistivity and phase transition thresholds of the PTM on the characteristics of Hyper-FETs. Our analysis shows that the ratio of insulating and metallic state resistivity ( $\rho _{\mathrm {INS}}$ and $\rho _{\mathrm {MET},}$ respectively) of the PTM needs to be higher than the ${I}_{{{\mathrm {ON}}}} /I_{{{\mathrm {OFF}}}}$ of its host transistor to achieve performance improvement in Hyper-FET. For a host transistor with $I_{{{\mathrm {OFF}}}} = 0.051\mu \text{A}/\mu \text{m}$ and ${I}_{{{\mathrm {ON}}}} = 191.5\mu \text{A}/\mu \text{m}$ , $\rho _{\mathrm {MET}} .cm and $\sim 7.5~\Omega $ .cm $ .cm is required to achieve proper device functionality with a boost in ${I}_{{{\mathrm {ON}}}}/{I}_{{{\mathrm {OFF}}}}$ . Additionally, we establish the ranges of phase transition thresholds that yield proper functionality of the Hyper-FETs considering different ${I}_{{{\mathrm {OFF}}}}$ targets. The methodology of choosing appropriate PTM geometry to achieve the target device characteristics is also described. We show that with proper design, Hyper-FETs achieve 94% larger ${I}_{{{\mathrm {ON}}}}$ at iso- ${I}_{{{\mathrm {OFF}}}}$ compared with a FinFET. We examine the circuit design aspects of Hyper-FET in part II.