Steep-Slope and Hysteresis-Free MoS2 Negative-Capacitance Transistors Using Single HfZrAlO Layer as Gate Dielectric.

Abstract

An effective way to reduce the power consumption of an integrated circuit is to introduce negative capacitance (NC) into the gate stack. Usually, negative-capacitance field-effect transistors (NCFETs) use both a negative-capacitance layer and a positive-capacitance layer as the stack gate, which is not conductive to the scaling down of devices. In this study, a steep-slope and hysteresis-free MoS2 NCFET is fabricated using a single Hf0.5-xZr0.5-xAl2xOy (HZAO) layer as the gate dielectric. By incorporating several Al atoms into the Hf0.5Zr0.5O2 (HZO) thin film, negative capacitance and positive capacitance can be achieved simultaneously in the HZAO thin film and good capacitance matching can be achieved. This results in excellent electrical performance of the relevant NCFETs, including a low sub-threshold swing of 22.3 mV/dec over almost four orders of drain-current magnitude, almost hysteresis-free, and a high on/off current ratio of 9.4 × 106. Therefore, using a single HZAO layer as the gate dielectric has significant potential in the fabrication of high-performance and low-power dissipation NCFETs compared to conventional HZO/Al2O3 stack gates.