Steady-State temperature field prediction for FPGA chips with reduced number of temperature sensors

Abstract

Obtaining the steady-state temperature distribution of FPGA chip is the basis to build the thermal monitoring mechanism for reliable system performance. Existing work employs the full-coverage strategy to measure the steady-state temperature distribution of chip. However, many temperature sensors make it more complex to manage and optimize the FPGA’s logic, which would degrade the performance of FPGA. To overcome the problem, this paper proposes a method with a reduction of 60 % sensors to achieve an accuracy close to the steady-state temperature field of the FPGA obtained by the full-coverage strategy. In this method, the temperature field prediction model of the chip is established with fewer measurement data to generate the chip’s steady-state temperature distribution. Experimental results show that the proposed method performs excellently at ambient temperatures from 25 °C to 150 °C, with the average absolute error of 0.49 °C. The proposed temperature sensor placement strategy ensures the measurement accuracy and the LAB utilization rate of FPGA is only 3.06 %. Additionally, the proposed method has good generalization ability for different number and placement of hotspots.