Abstract

This paper presents a blended analytical electrical–thermal model for steady state thermal analysis of through-silicon-via (TSV) in three-dimensional (3D) integrated circuits. The proposed analytical model is validated by the commercial FEM tool—COMSOL. The comparison between the results of the proposed analytical formulas and COMSOL shows that the proposed formulas have very high accuracy with a maximum error of 0.1%. Based on the analytical model, the temperature performance of TSV is studied. Design guide lines of TSV are also given as: (1) the radius of the TSV increases, the resistance decreases and the temperature can be increased; (2) the thicker the dielectric layer, the higher the temperature; (3) compared with carbon nanotube, the Cu enlarges the temperature by 34 K, and the W case enlarges the temperature by 41 K.

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