Statistically estimating path delay fault coverage in combinational circuits

Abstract

Presents a technique to statistically estimate path delay fault coverage. By partitioning a combinational circuit into non-overlapping fanout free logic cones, the authors accurately calculate the transition sensitization controllabilities of 0/spl rarr/1 and 1/spl rarr/0 transitions of the lines within a fanout free logic cone to the output of the fanout free logic cone for each fanout free logic cone. The detectability of a path delay fault is evaluated as the product of the observabilities of the input lane to its head gate within each fanout free logic cone on the path multiplied by the transition controllability of the path. As the estimation technique only requires fault-free simulation of a combinational circuit, it is efficient compared to accurate path delay fault simulation, and gives reasonably good path delay fault coverage estimation for the ISCAS85 benchmark circuits.