Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations

Abstract

The ongoing trends in technology scaling imply a reduction in the transistor threshold voltage (V/sub th/). With smaller feature lengths and smaller parameters, variability becomes increasingly important, for ignoring it may lead to chip failure and assuming worst case renders almost any design nonachievable. This paper presents a methodology for the analysis and verification of the power grid of integrated circuits considering variations in leakage currents. These variations are large due to the exponential relation between leakage current and transistor threshold voltage and appear as random background noise on the nodes of the grid. We propose a lognormal distribution to model the grid voltage drops, derive bounds on the voltage-drop variances, and develop a numerical Monte Carlo method to estimate the variance of each node voltage on the grid. This model is used toward the solution of a statistical formulation of the power-grid-verification problem.