Statistical Total Power Estimation Techniques

Abstract

For digital CMOS circuits, the total power consumption is given by the following formula: $$\begin{array}{rcl}{ P}_{\mathrm{total}} = {P}_{\mathrm{dyn}} + {P}_{\mathrm{short}} + {P}_{\mathrm{leakage}},& &\end{array}$$ (7.1) in which P dyn, P short, and P leakage represent dynamic power, short-circuit power, and leakage power, respectively. Most of the previous works on power estimation either focus on dynamic power estimation[116, 10, 29, 28,64,30] or leakage power estimation[13, 95, 200, 158]. As technology scales down to nanometer ranges, the process-induced variability has huge impacts on the circuit performance[120]. Furthermore, many variational parameters in the practical chips in nanometer range are spatially correlated, which makes the computations even more difficult[195], and simple assumption of independence for involved random variables can lead to significant errors.