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Abstract
We investigate the influence of grain size variations on device properties of polycrystalline silicon thin-film transistors (poly-Si TFTs) by drift–diffusion device simulations. Employing our grain boundary model which represents the intrinsic variations of grain size [Jpn. J. Appl. Phys., 42, L634 (2003)], the subthreshold characteristics are simulated for the various configurations of grains in the channel region so that the statistical fluctuation of device characteristics is investigated. It is shown that the variations in subthreshold characteristics are caused mainly by the number of grains included in the channel because the grain boundaries act as highly resistive regions. However, as the channel length shrinks, the grain boundary located close to the drain critically determines the channel resistance of poly-Si TFTs and the device characteristics could differ even if the number of grains included in the channel region is the same.
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