Statistical simulation of gate dielectric wearout, leakage, and breakdown

Abstract

We present a set of models for the simulation of gate dielectric leakage, wearout, and breakdown. The leakage model accounts for direct and trap-assisted tunneling through the dielectric layer. Wearout is caused by the leakage-induced creation of neutral defects at random positions in the dielectric layer, which, if occupied, degrade the threshold voltage of the device. Gate dielectric breakdown is triggered by the formation of a conductive path through the insulator. To allow trap characterization and for the simulation of fast transients the modeling of trap charging and decharging processes is outlined. The models have been implemented into a three-dimensional device simulator and are used for the characterization of ZrO 2 -based dielectrics and for the study of gate leakage and wearout effects in standard CMOS inverter circuits.