Statistical placement for FPGAs considering process variation

Abstract

Process variations affecting timing and power is an important issue for modern integrated circuits in nanometre technologies. Field programmable gate arrays (FPGA) are similar to application-specific integrated circuit (ASIC) in their susceptibility to these issues, but face unique challenges in that critical paths are unknown at test time. The first in-depth study on applying statistical timing analysis with cross-chip and on-chip variations to speed-binning and guard-banding in FPGAs has been presented. Considering the uniqueness of re-programmability in FPGAs, the effects of timing-model with guard-banding and speed-binning on statistical performance and timing yield are quantified. A new variation aware statistical placement, which is the first statistical algorithm for FPGA layout and achieves a yield loss of 29.7% of the original yield loss with guard-banding and a yield loss of 4% of the original one with speed-binning for Microelectronics Center of North Carolina (MCNC) and Quartus University Interface Program (QUIP) designs, has also been developed.