Statistical modeling of gate-delay variation with consideration of intra-gate variability

Abstract

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. The variation of each gate delay directly influences the variation of circuit delay, so it is important to characterize each gate-delay variation accurately. Our model characterizes the gate delay by transistor characteristics. Every transistor in a gate affects the transient characteristics of the gate, so it is indispensable to consider the intra-gate variability for the modeling of gate-delay variation. This effect is not captured in a statistical delay analysis reported so far. Our model characterizes a statistical gate-delay variation using a response surface method (RSM) and represents the intra-gate variability with a few parameters. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation.