Statistical modeling for efficient parametric yield estimation of MOS VLSI circuits

Abstract

Large statistical variations are often found in the performance of VLSI circuits; as a result, only a fraction of the circuits manufactured may meet performance goals. An automated system has been developed to obtain the process statistical variations and extract SPICE model parameters for a large number of MOS devices. Device length and width, oxide capacitance, and flat-band voltage are shown to be the principal process factors responsible for the statistical variation of device characteristics. Intradie variations are much smaller than the interdie variations, therefore, only the interdie variations are responsible for variations in circuit performance. This accurate and simple statistical modeling approach uses only four statistical variables, and thus enables the development of a very computationally efficient statistical parametric yield estimator (SPYE). A linear approximation for the yield body boundary is used to make an accurate prediction of parametric yield. With the addition of temperature and supply voltage as operating condition variables, a maximum of seven simulations are required; only slightly more than the three to five required for worst case analysis. The method has also been adapted statistical parametric specification of standard cells; performance ranges of circuit building blocks can be characterized once the statistical variations of process-dependent parameters are known. Predicted performance variations from SPYE have been compared with measured variations in delay and power consumption for a 7000-gate n-MOS inverter chain. Agreement with the mean delay and power are better than 5 percent where SPICE model parameters were obtained from the same slice used for circuit characterization. Excellent agreement was obtained in the predicted spread in the circuit delay and power consumption using measured variations in the statistical variables.