Statistical Gate Sizing for Yield Enhancement at Post Layout Level

Abstract

The aggressive scaling of technology parameters in deep submicron (DSM) circuits has led towards an increased impact of process variations on delay and crosstalk noise. In this work, we develop a new post-layout gate sizing algorithm for simultaneous reduction of delay uncertainty and crosstalk noise under the impact of process variations. The problem of post-layout statistical gate sizing is modeled as a 2-player stochastic game and solved using Nash equilibrium theory. Due to process variations, the gate sizes are no longer deterministic, but rather behave as a probabilistic distribution over a range. Stochastic games allow the modeling of probabilistic distribution of gate size space and also effectively capture the conflicting nature of the problem. The authors implemented two different strategies in which the games are ordered according to (i) the noise criticality, and (ii) the delay criticality of nets. Experimental results demonstrate the effectiveness of the developed methodology by improving both delay and crosstalk noise violations, resulting in improved yield when compared to the deterministic approach without area overhead or the need for rerouting.