Abstract
The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2\ \mu {\rm m} process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.
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