Abstract
A statistical switch-level simulator, based on interval and statistical analysis techniques, that simulates the effects of fabrication process fluctuations and environmental effects on digital CMOS integrated circuits is presented. The simulator is computationally very cost-effective compared to conventional Monte Carlo simulators, yet produces results with equal accuracy. The simulator enables analysis of the sensitivity of critical function and performance levels to a variety of parameter variations, thus providing a basis for establishing correspondence between process control, yield, and reliability. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
