Statistical clock skew modeling and analysis for resonant clock distribution networks

Abstract

Resonant clock is a new design technique for clock distribution that is gaining prominence in the design of low power and high frequency digital designs. To evaluating the performance of resonant clocks, a statistical clock skew modeling for resonant clock distribution network is presented in this paper, supporting the design of low power, skew, and jitter resonant H-tree clock distribution networks. This paper applies the models to two case designs of a two-level resonant H-tree network and a two-level nonresonant H-tree network, distributing a 5-GHz clock signal in a 0.18-um CMOS technology. The Monte Carlo simulation results exhibits that a two-level resonant H-tree network can achieve an 64% decrease in clock skew and a 65% decrease in clock jitter as compared to a nonresonant H-tree clock distribution network. In the paper, the clock skews between leaf nodes hardly do not vary with the power supply noise for resonant clock is first found. Statistical jitter simulations also show that resonant clock distribution networks have optimal clock jitter with special load.