Abstract

Line-to-line leakage, ramped voltage stress and time-dependent-dielectric-breakdown are widely used to characterize the reliability of low-k dielectrics in the back-end-of-line. Conventionally, ramped voltage stress is used to determine the breakdown voltage (V/sub BD/) distribution across the wafer. Also, it is able to screen out defect-related breakdowns within seconds besides monitoring process uniformity across a wafer (Jow et al., 2003). On the other hand, TDDB is mostly used to predict lifetime of a component, adopting either the E-model for an extrinsic mode of failure at low electric field range or 1/E-model for an intrinsic mode of failure at high electric field range. Important information can be obtained from voltage ramp tests besides the conventional breakdown voltage distribution. Conduction mechanisms such as Schottky and Pool-Frenkel emission in carbon-doped silicon oxide IMD were reported by Yiang et al. (2003), The possible leakage pathways were also deduced from the conduction mechanism analysis (Ngwan et al., 2004). We propose that additional information from the voltage ramp tests can be obtained and that is the identification of extrinsic and intrinsic breakdown mechanisms.

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