Statistical Analysis of Soft Error Rate in Digital Logic Design Including Process Variations

Abstract

The susceptibility of digital systems to single event transients becomes increasingly severe with CMOS technology scaling, and transient faults analysis becomes more and more important. As technology scales further in sub 40 nm, process variations present another major design challenge, which makes the transient faults analysis more complicated. To address process variations, this paper presents a statistical soft error rate (SER) analysis method based on modified response surface modeling and artificial neural network modeling. Experimental examples show that the proposed method provides fast and accurate SER estimation. The results have shown that the process variation has significant impact on the SER and use of only a static SER analysis will generally underestimate the circuit SER.