Abstract
Multilevel cell (MLC) Resistive Random Access Memory (RRAM) is an attractive technology option to realize ultra-high density, low-power memory arrays. Traditional 1-transistor 1-resistor (1T1R) bitcell suffers from adjacent state overlap due to the inherent RRAM variations which hinders the realization of MLC capability. In this work, we evaluate an alternate 2-transistor 1-resistor (2T1R) gain-cell RRAM bitcell topology that has higher read-out dynamic range and exhibits higher process variation tolerance compared to the baseline 1T1R bitcell.
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