Static range testing of ADC

Abstract

This paper discusses the viability of Time Tick based Built In Self Test (TT BIST) implementation using the binary “hot” values of the Analog to Digital Converter (ADC) output for ADC testing. In traditional methods histogram testing is done using sinusoidal signals. But such testing methods are quite slow for high resolution ADCs. The proposed method uses dynamically generated ramp signal using current source with digital switch for selecting the various combinations of the binary “hot” values thereby minimizing the test vectors for computation of the INL and DNL errors. Thus by choosing only the binary onehot, threehot, fivehot and sevenhot values yields the minimum variance of the static errors from the benchmark results and hence the number of clock ticks during the transition between these “hot” values are determined and compared with the ideal number of ticks between those levels using the TT BIST method. The entire computation is done in a single ramp cycle and since this modified TT BIST method uses only 20 “hot” levels of digital output instead of all the 256 levels of an 8 bit ADC, the testing time is reduced with the desired accuracy levels being achieved with the TT BIST method.