Abstract
In this paper, we describe and analyze the performance of a new architectural construct - an efficient synchronization mechanism called "Static Barrier MIMD" or SBM. Unlike traditional barrier synchronization, the proposed barriers are designed to allow static (compile-time) code scheduling to eliminate some synchronizations. The static barrier MIMD hardware is more general than most hardware barrier mechanisms, allowing any subset of the processors to participate in each barrier. The barriers execute in a small number of clock ticks, and processors proceed simultaneously past the barrier. The performance of idealized barrier schedules is examined to gain insights into code scheduling for barrier MIMD machines.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
