State Feedback Design Approach for Fast Recovery Digitally Current Mode Controlled Boost Converters

Abstract

The existence of a right-half-plane (RHP) zero in the control-to-output transfer function of a CCM (continuous conduction mode) boost converter significantly restricts the achievable control bandwidth ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> under high load current and/or voltage gain conditions when the RHP zero comes closer to the imaginary axis of the complex ‘s’ plane. Current mode control (CMC) offers superior bandwidth over voltage mode control; however, ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> is still restricted to ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rhp</inf> /3 while designing a type-II voltage compensator using an output feedback (OF) design approach. A higher ω <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</inf> results in a poor phase margin, resulting in a higher voltage overshoot during a step-up reference transient. The scenario becomes more severe under digital CMC (DCMC) due to the sampling delay which further degrades the phase margin. This paper proposes a discrete-time state feedback (SF) design approach in a DCMC architecture, which significantly improve the transient performance. Using a discrete-time modeling framework, closed-loop stability analysis and controller design are carried out using both the OF and SF design approaches. Thereafter, comparative simulation case studies are shown to demonstrate the superiority of using the SF approach over the OF solution. Experimental results are presented for a synchronous boost converter with 500 kHz switching frequency.