State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis

Abstract

Finite State Machines are often used to design control circuitries which need to be highly testable and should consume very low power. FSM decomposition, state encoding and partitioning are the most effective techniques for achieving low power. However, selection of suitable polarity of output and state bits while state assignment is yet another avenue for achieving low power which has been explored in this paper. In first part of the paper, we have included all these key ideas-partitioning, state encoding and output polarity in the synthesis process and applied Genetic Algorithm (GA) to find an optimal solution for low dynamic power FSM synthesis. Next, we have incorporated a unique scheme of partitioning and state assignment for high testability, and formulated another GA, wherein we have minimized the state dependencies in order to reduce the number of feedback paths in the FSM for the ease of testability. After exhaustive experimentation with several benchmark FSM circuits, we find an average power reduction of 28.67% over state assigned by NOVA. Moreover, we have also carried out a power-testability trade-off and have seen superior fault-coverage with the proposed GA based technique over NOVA.