Stacking Technique of Known Good Rebuilt Wafers Without Thru-Silicon Via Commercial Applications

Abstract

The 3D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc... for the Hi-Rel field (space, defence, medical, industrial). A stacking technique of all types of bare dice has been developed. The various manufacturing steps as well as the main applications will be presented. This technology is extremely robust (-130degC + 175degC, 40000 g, resistance to humidity, etc...). The modules are qualified by all worldwide most important space agencies: CNES, ESA, NASA, JPL, ISRO... A technological breakthrough started in 2001; it consisted in another 20 to 30 reduction factor of the weight and volume of these 3D modules. From 2001 to 2005, an important European program WALPACK, funded up to 20 Meuro with St Microelectronics, CEA/LETI, Thales, and 3D Plus has allowed to establish the feasibility of a stacking technique totally wafer level process. A trademark registration wirefree die on die (WDoD) has been made for this process. The prototyping and pre series have been realized thanks to an agreement between 3D Plus and Philips semiconductors, now NXP. This wafer level stacking technique has been named wireless die-on-die (WDoD). It is based on the criteria which we used in the 1990 when we launched our mature and fully qualified 3D technique. This new approach of wafer stacking without thru-silicon via therefore allows to stack any type of standard dice, whatever their sizes. It additionally allows to stack 10 levels per mm (100 mum per levels). The area is given by the larger die plus lOO mum of polymer (epoxy resin) around it. A development is in progress with the most worldwide important manufacturer of small cards in order to integrate 5 levels of dice (including a MEMS) within a 500 mum thickness for SIM cards applications. Applications which will be presented concern the smart cards, and particularly the SIM cards. As a matter of fact, memories capacities of the SIM cards will be significantly increased and we build modules comprising 4 FLASH memories plus the secure microcontroller within 500 mum, in order to place this module within the 800 mum thickness of the SIM card (Mega SIM). Applications with MEMS in order to build abandoned with energy, antenna and communication functions are developed for avionics and industrial areas. In conclusion, this full wafer level process does not need TSV and stays versatile; It will allow to build smart sensors at very low costs, since the utilizes some of the steps used in the building of wafers and totally parallel processing from A to Z. A short comparison between the Package on Package'ToP and the WDoD is given. It can be seen that the test and burn- in of one or two sub systems like in PoP can easily be made but in fine, the volume of the module is much smaller.