Stacking Faults and Stress Memorization Technique Study for n-Type MOSFET Performance Improvement in All Last High-k Metal Gate Process Development

Abstract

In this paper, the stacking faults, stress memorization technique (SMT) and their impacts on n-type MOSFET device performance were studied. SMT combines source/drain deep PAI improves short channel device electron mobility 25%, Ion/Ioff curve 8% and long channel device 10% and 4%, respectively. A mechanism why SMT improves device performance in all last HKMG (High-k Metal Gate) process was proposed. During SMT anneal, poly expands much more than the hard nitride cap, the thermal stress gain from poly transformation from an elastic state to a plastic state was transferred into the channel, the stress was then memorized by the source/drain stacking faults, that were formed during the SMT anneal at deep pre-amorphous source/drain area. After poly removal, the tensile stress still exists, as it was retained by the stacking faults. The stress intensity along channel, Sxx, is the key parameter to index the stress effect on device performance improvement; it is related to poly volume and gate length. And based on this, the reasons that long channel and short channel devices performance gain are much smaller than that of the middle channel devices were also discussed.