Abstract
For 3D Si die to Si die stacking and connections between Si die and Si interposer, fine pitch microbump interconnections are needed next to TSV's. When scaling the pitch below 40μm, stacking accuracy is one of the main drivers to ensure yielding devices. Stacking tolerance are being discussed in the view of scaling. It is shown that stacking can be made less sensitive to misalignment by playing with the bump diameters. In the vertical direction, stacking tolerance can be increased by bump planarization or reflow. The demonstrated results are mainly based on CuSn-Cu microbumps but the discussed theory is generic, it is not restricted to this kind of interconnection.
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