Stacked-Switch Power Factor Correction Architecture

Abstract

Two-stage power factor correction (PFC) architecture, consisting of a boost PFC front end and an isolated DC–DC converter, is widely used in AC–DC applications. However, the boost PFC front end loses zero-voltage-switching (ZVS) at high-line conditions, limiting its practical switching frequency. Consequently, a relatively large boost inductor and EMI filters are needed in the two-stage architecture, leading to a lower power density design. This article proposes a stacked-switch PFC architecture that allows all switches to achieve full-load-range ZVS at a universal input while reducing the component counts compared to the two-stage architecture. As a result, the stacked-switch architecture can operate efficiently at a much higher switching frequency than the two-stage architecture, allowing for higher power density and lower cost. Additionally, this architecture can be operated at a constant switching frequency, which is beneficial for simplifying the magnetics and controller design. A 150-W-universal-input prototype is built to verify the effectiveness of the stacked-switch PFC concept. The prototype measures 92.9 % peak efficiency and 53.9 W/in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$^{3}$</tex-math></inline-formula> power density by box volume.