Stacked Transformer: Influence of the Geometrical and Technological Parameters

Abstract

In this work, we study the effect of the geometrical and technological parameters on the performance of stacked transformer in crystal metal oxide silicon (CMOS). It also presents the equivalent electrical model of on-chip stacked transformer based on the “2-p” architecture and contains the equations to evaluate its components values. These equations depend on both technological and geometric characteristics of the transformer. The inductance (primary or secondary) and the quality factor (primary or secondary) of on chip stacked transformer depend on the geometrical and technological parameters. We study the effect of the geometrical and technological parameters of on chip transformer, so to establish a methodology of its dimensioning and consequently its integration in a chip. The various geometrical and technological parameters that influence the performance of the transformer: capacitance between primary and secondary coils, oxide capacitance between the (primary coil, secondary coil) and substrate, substrate ohmic loss, and substrate capacitance.