Stacked oxide as trench gate dielectric

Abstract

Stacked chemical‐vapor‐deposition (CVD)‐thermal oxide, consisting of a CVD oxide deposited over a thin thermal oxide and followed by a post‐deposition anneal in oxygen, is proposed as a gate dielectric in trench technology. In contrast to thermal oxide, it is possible to deposit the CVD oxide uniformly around the trench corners, and low‐temperature CVD processes are available. In this report, we discuss the fabrication and characterization of metal–oxide–semiconductor trench capacitors with both thermal and stacked oxides as dielectrics. In addition, planar capacitors are investigated for comparison. It is shown that, in the trench capacitor, the stacked oxide has similar behavior to the thermal oxide in terms of fixed oxide charge and interface state density. There is, however, a dramatic improvement in the charge to breakdown (Qbd) for the stacked oxide in the trench capacitor. Based on the comparison between planar and trench capacitors as well as between stacked and thermal oxides, it is speculated that the much lower Qbd in the thermal oxide may result from a weak spot localized at the trench corners due to high stress generated during thermal oxidation, in addition to the reduced oxide thickness.