Stacked Low-Inertia Converter or Solid-State Transformer: Modeling and Model Predictive Priority-Shifting Control for Voltage Balance

Abstract

This article presents control challenges of stacked low-inertia converter (SLIC) or cascaded reduced dc-link solid-state transformer (SST) and proposes a novel model predictive priority-shifting (MPPS) control with implicit modulator and a discrete-time large-signal model for voltage balancing and dc-link regulation. Low-inertia converters, featuring small electrolytic capacitor-less dc links, dramatically reduce cost, size, and weight compared to conventional solutions. However, without a large dc-link buffer, the input and output are tightly coupled, leading to significant control challenges. The control becomes even more challenging with these converters stacked input-series output-parallel (ISOP) for medium-voltage (MV) grid, which causes coupling between the modules besides the coupling within each module. This article analyzes the multiobjective, multidegree of freedom control problem, using the modular soft-switching solid-state transformer (M-S4T) as an example of the SLIC. First, distribution of control efforts under controller saturation is critical because multiple control objectives can be conflicting, especially when the module voltages are unbalanced and are being restored. The MPPS can shift the priorities to address this issue. Second, due to the low inertia and high dc-link ripple, classic space vector pulsewidth modulation, average model with small-ripple assumption, and control design based on small-signal model cannot accurately modulate, model, and control the nonlinear reduced dc link. Therefore, a discrete-time large-signal model of the M-S4T is established to derive the predictive control in the MPPS. The MPPS and the PI control are compared in MV simulations to show the issue of applying the PI to the SLIC and the effectiveness of the MPPS for voltage balancing and dc-link regulation in a deadbeat manner. Finally, the proposed control is tested on a 5-kV ISOP SiC SST prototype to verify priority shifting to address controller saturation issue and fast and robust voltage balancing.