Stacked Ge Nanosheet GAAFETs Fabrication and Strain Effects Measurement

Abstract

Horizontally stacked Ge nanosheet GAA FETs are demonstrated, although Si, SiGe and GeSn stacked nanosheet FETs have been reported. The problem for formation of stacked pure-Ge nanostructures is that the Ge material is weaker than other IV group materials, and securing Ge material by selective etching away other IV group materials is difficult. In this work, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of material properties between Ge/Si is beneficial to the following selective etching process. In order to avoid island growth, Ge/Si multilayers must be grown at a low temperature. For selective etching, we found that, at a proper temperature and with assistance of megasonic agitation, the Si layers can be easily etched away over Ge layers with good selectivity by TMAH solution. Additionally we found the dislocations in suspended Ge sheets are more easily to remove than the case that Ge layers are still tied with Si layers. Finally, the devices with gate length of 80nm were fabricated, and current of over $1650\mu A/\mu m$ (per width of channel footprint) was achieved.