Stabilizing DPWM Current Mode Cascaded DC-DC Converters in DC Nano-Grid Without Clock Sharing

Abstract

In a two-stage intermediate bus architecture (IBA) consisting of an intermediate bus converter (IBC) followed by a point-of-load (PoL) converter, switching frequencies f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sw</inf> of individual converters may not be commensurate with each other in absence of clock sharing due to lack of communication. This paper shows that a fractional multiple of f <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sw</inf> among both the converters may eventually lead to sub-harmonic oscillations in the IBC, even when individual stand-alone converters are perfectly stable. Further, two compensation techniques are proposed in a digitally current mode controlled (DCMC) IBC to mitigate fast-scale instability without compromising the transient performance. The methods include (i) a digital moving average filter with the sampled output voltage of the IBC and (ii) adjustment of the offset with the sampled inductor current of the IBC. Both the proposed circuits can be easily implemented in a digital platform, which are disabled during a transient recovery. A hardware prototype is made with 50W power ratings for individual converters, and the analytical predictions using the proposed compensation techniques are verified experimentally.