Abstract
Graphical techniques for analysis of the stability and soft error rate (SER) of static RAM cells have been developed. These techniques include important transient effects and make readily visible the impact of variations in design approaches and parametrics. The techniques are illustrated with application to a high-speed 64K NMOS RAM and comparative cases. The stability and SER is sized for these cases as a function of design and parametric variations in timing approaches, device sizes, threshold mismatches, load resistors, and usage statistics. These variations can result in orders of magnitude variation in SER. Nevertheless, with careful design, 64K NMOS RAM cells can have reasonable stability and SER. Even if load resistors are not used, these SER can be much lower than might be expected by simple analogy to a one-device dynamic RAM cell with the same size storage capacitor.
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